ASIC and FPGA development teams frequently use third party IP in order to reduce product development time. When a company purchases IP, it is typically delivered in two pieces:
- A Bus Functional Model (BFM) or behavioral model for verification, and
- An obfuscated synthesizable RTL model (ASIC or FPGA) or implementation files (FPGA) for silicon.
The problem many users face is that the IP often behaves differently between simulation and silicon. This is due to errors in the BFM, lack of detailed functionality in the behavioral model, implementation errors (Synthesis, Place & Route), or model version differences. All of these issues are impossible to discover until the engineer attempts to get the design running in the system with the actual FPGA. While debugging IP issues in the system used to be a manageable problem, FPGAs have become so complex that debug times for each issue can take weeks to resolve.
The solution is to verify and debug the IP with the native FPGA device integrated into the simulator. GateRocket's RocketVision debug environment automatically identifies any differences between the chip and the simulation model and saves you weeks of needless debugging in the lab.