Would you ever attempt to bring up a complex system without first unit testing the major sub-functions? Probably not, because you know how hard it is to debug a system when there are hundreds of potential problems mixed together, and it's not clear which engineer "owns" the issue. The same holds true for complex FPGA-based systems on a chip (SoCs). If you wait until system-test to see if all the blocks work together correctly in silicon you may spend weeks/months trying to localize the subtle implementation problems that may result from IP, synthesis, or connectivity errors.
With GateRocket you can actually test each individual RTL block all the way to its silicon implementation- before you try to run the whole chip in the system. You simply take your block-level testbench and simulate it against the RTL block mapped to the RocketDrive native FPGA hardware. In this way you can make sure that each block behaves the same way in RTL and silicon representations and automatically detect any divergence in results between the two representations. Then you can debug any differences in the simulator where you have full visibility into the block and it is much easier to localize the source of the error. This can save you weeks or months of finger-pointing and painful debugging in the lab.