DV Con 2005 Verification and Debug Presentation
Posted by Dave Orecchio on Mon, Feb 14, 2005 @ 02:16 PM
GATEROCKET PRESENTS INNOVATIVE CONCEPTS AT DVCON
- MERGING ASIC AND FPGA DESIGN TECHNIQUES TO CUT DESIGN TIME -
Bedford, Massachusetts, February, 2005: GateRocket, Inc. today announced participation in DVCon and the presentation of a paper titled MERGING ASIC AND FPGA DESIGN TECHNIQUES TO CUT DESIGN TIME. The paper will be presented by GateRocket Founder Chris Schalick on Tuesday February 15th in Session 6 - Advances in Design.
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