RocketBlog - a discussion about all things related to FPGA verification and debug

FPGA Survey Highlights Debug Crisis

The popular web site and newsletter FPGA Journal conducted a survey of its readership in the spring of 2010 to determine the biggest issues in verifying and debugging complex FPGAs today. Over 300 FPGA designers and managers responded to the survey, citing the bottlenecks they face as they try to bring up today's most advanced FPGAs.

The survey produced some eye opening results, particularly among the segment of the survey population doing complex FPGA design. On average, the number of iterations required to bring up a working FPGA is more than 100, a situation unheard of in previous eras of FPGA use, and one that is threatening the biggest FPGAs to being with – faster time to market and/or rapid prototyping.

The survey revealed that the number one issue causing lengthy debug times is tracking down errors in RTL code. This can be a result of designer error, or, increasingly, because of issues related to other design tools such as synthesis and place and route, or IP cores. Regardless of the source, these types of errors are tougher and tougher to find using traditional FPGA debug and verification techniques.

In fact, the survey results show that debugging a complex FPGA can now represent to 92 days of the overall development cycle!

If you are having issues with FPGA debug and verification, you are not alone. Of course, we believe GateRocket can help address this growing crisis with our solutions for giving designer increased visibility into their FPGA design through our unique Device Native approach.

To see for yourself what other designers are experiencing, go here to sign up for a 7-page summary of the survey results

EDA Cafe on GateRocket at DAC 2010

Dave Orecchio, GateRocket CEO disucsses recent trends in the FPGA market and the recent introduction of their RocketDrive for Xilinx Virtex-6 devices. 

This video was recorded by EDA Cafe' editor Graham Bell at the Design Automation Conference in June, 2010. 

Xilinx 7 Series: A game changer for FPGAs?

Last month Xilinx took the wraps off its next generation FPGA family, the 7 Series.  There were many exciting advancements included in the roadmap laid out by the company as it moves its state of the art devices to 28nm (on TSMC and Samsung processes). For us at GateRocket, we are impressed with the huge leap in capacity that the move to 28nm will enable – in some cases doubling the amount of logic gates for designers to work with. Virtex7, for example, offers 2 million logic cells. With that kind of capacity, it is inevitable that the verification and debug challenges for FPGA designers will require an advanced and efficient approach. More on that in a bit.

First a recap of the 7 Series.

Interestingly, the Xilinx FPGA family now consists of three components, instead of the traditional Virtex/Spartan product lines. The new triumvirate consists of Virtex at the high end, and newly named Kintex as the mid range option, and Atrix as the lower cost alternative. It’s good to see Xilinx continue to expand the number of options and overall flexibility for its product line, tailoring the products for specific needs like cost, performance, power, etc.

Family naming conventions aside, the technology under the hood of the new architecture and devices is impressive. First of all, Xilinx continues its Targeted Design Platform strategy with the 7 Series, which helps designers optimize FPGA for special applications like wireless or broadband or DSP. The new family looks to offer a smooth transition path from previous generations Xilinx devices, too.

Most importantly in terms of breaking into new markets, Xilinx appears to have cracked the code on delivering truly low power solutions for programmable devices. The new family reduces power by up to 50% over previous generations, positioning it very well for demanding consumer and mobile markets that require low power consumption characteristics. In fact Xilinx CEO Moshe Gavrielov says that with the low power capabilities of the 28-nm family, the market opportunity for FPGAs could be twice as large as what is if for the current 45/40nm generation. With the combination of low power, high capacity, and targeted design strategy, Xilinx thinks it can break into markets like LTE basebands, automotive infotainment and more advanced medical applications, for example.

As FPGAs continue their march along the Moore’s Law curve, the needs for specialized and powerful design tools becomes clearer and clearer. The 7 Series is a great advancement and we are excited to be part of how it will transform FPGAs as we know it.  For those of you who may not be familiar with our solution, because we use the FPGA to test the FPGA and leverage the vendor tools to place the design into the RocketDrive, we are able to leverage all of Xilinx R&D when we deliver new RocketDrives based on the new family of devices. 

In essence, we can offer a solution as soon as the devices are available and we start to see customer demand for them. With our recently-announced support of the Virtex-6 family already seeing much interest in the market, we are excited to move along the technology curve with the FPGA suppliers and let our mutual customers leverage the great potential these devices now offer.

DAC 2010 update: Smaller crowds but interest in FPGA design is high

ANAHEIM, Calif. -- As the 47th Design Automation Conference winds down, we can reflect on this year's annual gathering of the chip design industry. The announced conference attendance was lower than previous years for sure, and we can assume several factors played a role in that drop-off: the economy, reduced travel budgets, and the variety of events and other ways designers can get information about new products (such as our own webinar series that we offer on a regular basis). That said, DAC is still ‘the' place to meet customers, partners, press and other important people that help shape the future of electronic design.

For GateRocket, it was a good show. Our booth was busy as we demonstrated the new capabilities of our RocketVision software and new versions of our RocketDrive hardware. The people that did come by our booth were well-qualified and had a keen interest in how we can help reduce verification time for them.

Our observation is also that FPGA use continues to expand beyond their traditional role as prototyping platforms. The increases in performance and capacity of the latest devices form Altera and Xilinx make them more than suitable for a wide range of production applications. Add in the time to market and programmability benefits of FPGAs, and designers and their management are truly responding to the ‘programmable imperative."

DAC is always a great opportunity to hear first hand what people are concerned about, and certainly verification is tops among the issues with FPGA designers. We met with several FPGA users who are very excited about the relief that our products can bring and we look forward to helping them and others make an impact on their design cycles.

It was nice seeing all of friends in the industry, too - people from Altera, Xilinx, the EDA companies and the press and bloggers who follow the latest developments in chip design. We look forward to seeing every one again next year in San Diego.

DAC Panel: Specialized FPGA tools needed to keep up with size and complexity

ANAHEIM, Calif. - A Pavilion Panel at DAC, entitled "Is the FPGA Tool Opportunity an Oasis or Mirage?" raised the question about the need for more specialized and sophisticated tools for FPGA design. The answer from the panelists was a resounding "yes".

The panel was smoothly moderated by FPGA Journal editor Kevin Morris and brought together a trio of experienced FPGA tool experts - representatives from Mentor Graphics (Simon Bloch), Synopsys (Andrew Dauman) and US Venture Partners (Jacques Benkoski). There was universal agreement that given the complexity of modern FPGAs, design tools must keep pace, especially in areas such as verification and synthesis.

The panelist acknowledged that the tools offered by the FPGA vendors themselves served users well for the first several generations of FPGA devices, but with those same silicon providers significantly improving their devices with each new generation, tool performance and efficiency needs a boost. They debated whether those tools should continue to come from the FPGA vendors themselves and again there was agreement that the likes of Xilinx and Altera need to focus on their core competence of the underlying ‘platform' or fabric of their devices, and that there was an opportunity for specialized tool suppliers to help address the growing challenges in the design flow for FPGAs.

The panel likened the current state of FPGA to the adolescent days of the ASIC industry when the first suppliers of those custom devices also offered their own tools, often for free. But as ASIC complexity and size increased, it became clear that more advanced tools were needed and this played a large role in the evolution of the modern EDA industry.

Similarly, the days of FPGA designers relying on free tools are numbered, especially at the high end of the market. "Free is a four-letter word that begins with F," joked USVP's Benkoski, emphasizing that, in the end, a free tool may be more costly to a design team or company if it causes longer design cycles or can't handle the complexity of a design.

The EDA suppliers agreed, noting that a commercial tool will almost always be a wiser investment for a high-end design project considering the breadth of use and testing it gets across multiple customers, and the fact that supporting an in-house tool is an overlooked cost and headache that many companies overlook.

At GateRocket we agree with this sentiment, having seen first hand the need for more powerful verification and more efficient debugging capabilities by FPGA designers. Our exclusive focus on FPGA verification and debug allows us to hone in on the specific issues FPGA designers face (remember our founder was an FPGA designer himself!) and develop solutions that are optimized for the unique requirements of today's most advanced FPGA devices.

Live from DAC 2010: Gary Smith on What's Hot

ANAHEIM, CAlif. - One of the highlights of the Design Automation Conference every year is Gary's Smith "What's Hot" list. He spends the year trolling through EDA vendors' pitches, both large and small companies, to find the most interesting new technology available for chip designers. A daunting task considering the number of new start-ups emerging all the time, not to mention the large EDA vendors that continue to come out with add-on products.

But Gary carries on, and always comes up with a pretty complete and compelling list of things to see. He breaks the new innovations down into logical categories - physical design, verification, DFM, etc. etc. He even produces a wall chart that displays all the different types of EDA tools and technologies available, and all the EDA vendors who provide tools in each bucket.

GateRocket was pleased to be included in Gary's very exclusive list of "Must See" new technologies at this year's DAC. Gary presented his list last night at a special welcome reception hosted by EDAC, and then again this morning on the DAC show floor. Both presentations drew large crowds of designers, anxious to see what's new and exciting this year.

Gary spent a bit of time talking about how GateRocket has evolved from being an emulation/hardware company, to offering a complete debug and verification solution that consists of the RocketDrive hardware as well as the newly enhanced RocketVision software debug environment. He highlighted the new SoftPatch features in the new release 5.0. And, he stressed the criticality of enhanced verification and debug for FPGAs in general.

We're glad Gary is on board with what we see as a growing crisis in FPGA design, and we thank him for including GateRocket in his prestigious list.

See you at DAC 2010

The Design Automation Conference is always a great event to catch up with people in the industry - customer, partners, press, other EDA suppliers. We're expecting next week's 47th edition of the annual chip design confab, to be held in Anaheim, to be no different, albeit perhaps less crowded than the glory days of years gone past.

For GateRocket, it's an opportunity to show the world the latest solutions we have to address the most pressing FPGA design verification debug challenges. Front and center of our exhibit will be our Release 5.0 of our RocketVision debug solution, featuring the highly efficient SoftPatch feature. SoftPatch eliminates the majority of long loops through synthesis and place and route by enabling interactive exchange of RTL and device-level design representations within the user's software simulator without rebuilding the FPGA.

Our RocketDrive verification tool comes in new flavors now, with support for Xilinx' Virtex-6 devices being offered now (to go along with Virtex-4 and Virtex-5, and Altera's Stratix II and IV families). In fact, we've introduced a tiered pricing model for RocketDrive, which leverages our unique Device Native approach to speeding up verification performance.

We're honored that we are once again on Gary Smith's "What to see @DAC" list, which he will present on Monday morning at 9:00AM in Booth #694.

Come see us in Booth #1319. We'll give you a copy of the recent FPGA Journal survey that shows where the growing pain points are in the FPGA design process.

We'll also be telling our story in the DAC Exhibitor Forum. That's located in Booth #1562 and we'll be on stage on Wednesday at 3:55PM.

Finally, if you want to hear and chime in on a debate about the future of FPGA tools, we recommend going by the panel entitled "Is the FPGA tool opportunity an oasis or mirage." This will be held in Booth #694 at 2:30 on Tuesday and will be moderated by FPGA Journal editor Kevin Morris.

Hope to see many of you at DAC 2010, and if you come by our booth, we'll make sure you take a rocket home from Anaheim!

Not your father's FPGAs

The current generation of modern FPGAs have reached unprecedented levels of performance, size and complexity. Devices like those in the Xilinx Virtex®-6 family, for example, are built on the most advanced manufacturing processes (45nm and 40nm) and allow true system-on-chip integration featuring embedded processing cores that enable the most bandwidth-demanding applications.

In addition to the performance advantages, devices in the Virtx-6 family consume 50 percent less power and deliver 20 percent lower cost than the previous generations. The latest family is built with a mix of programmability, integrated blocks for digital signal processing (DSP), memory, and connectivity support - including PCI Express(R) 2.0 compliant interface blocks and high-speed transceivers supporting line rates beyond 11Gbps to satisfy the insatiable demand for higher bandwidth and performance. These advances enable system architects to integrate Virtex-6 FPGAs into their designs to enable 'green' central offices and data centers, which is particularly relevant for the telecommunications industry as it deploys new technologies to support the demand for internet video and rich media content.

Clearly, these are not your father's FPGA's anymore.

With the great benefits and capabilities of today's most sophisticated FPGAs come a new wave of design challenges. At GateRocket we are focused exclusively on the debug and verification issues associated with these mammoth devices.

That's why we are pleased to offer a new version of our verification solution that incorporates FPGAs from the Xilinx Virtex-6 family. Using GateRocket's RocketDrive system, designers can now literally integrate the Virtex-6 FPGA into their HDL simulator to provide a "hardware in the loop" process based on GateRocket's proprietary Device Native® methodology. This has proven to cut verification and debug time half versus traditional FPGA design approaches. By combining the actual FPGA hardware and RTL simulation models in the same verification run, this solution reduces verification time significantly.

Advanced debugging with RocketVision® for Virtex-6 devices
In addition to the performance boost the RocketDrive system provides, the GateRocket solution also allows designers using Virtex-6 devices to move effortlessly between RTL and the specific FPGA being targeted, combining actual FPGA hardware and RTL simulation models together in a single verification run, without changes in the design flow or methodology. This technique, called soft patch, provides engineers with the ability to make a change to one or more RTL blocks and re-run them along with the hardware implementations of the other blocks, thereby avoiding the need to rebuild the device for each fix and enabling multiple design-change-debug iterations in a single day. The net result is a time savings of up to 50% or more over traditional verification and debug approaches.

Multiple configurations optimized for different user needs
The new Virtex-6 RocketDrives use the largest LX and SX devices for advanced logic and DSP applications respectively. GateRocket also offers a cost effective mid-range device configuration targeted at users who do not require the largest FPGA device in the family. By using devices optimized for specific needs, GateRocket can pass along the cost savings for an even greater return on investment. Each RocketDrive configuration offers the same enhanced verification performance and debug efficiency, and maintains complete compatibility with popular EDA logic simulators from Cadence, Mentor and Synopsys.

Is FPGA's progress threatening to undermine programmability's greatest benefit?

 {The following is an excerpt from a blog post by noted industry veteran Jim Hogan. The full version of the blog is on the System Level Design site.}

Gary Smith, the noted EDA industry analyst, wrote an interesting blog post recently. In that blog, he spoke about the progress the FPGA suppliers have made in adopting new processes, thus offering a more robust design platform. In fact, new product families such as the Virtex-6 from Xilinx are taking market share from traditional ASIC design starts and becoming a more viable end-product alternative. There are many reasons for this. One of the most significant is the cost of delivering a leading edge ASIC. If FPGAs can meet the market requirements in terms of cost, performance and power, they are a great alternative to the ASIC without the silicon risk.
Their capacity, performance and even lower costs have made more than a few companies think seriously about leveraging the benefits of programmability in a more widespread way and not just looking at FPGAs as prototyping platforms.

But Gary sounds a note of caution by saying, "There is no free ride for the FPGA designer." It is true that by upping the ante on the capabilities of their FPGA devices, the silicon suppliers have thrown down the gauntlet from a design standpoint. New methodologies and tools - true system-level approaches like we have seen for hardwired gate arrays - will be required. Gone are the days of the free FPGA tools from Xilinx and Altera doing the job.

As with most areas of design automation, verification has become the major bottleneck. For FPGAs it comes down to two issues, performance and efficiency of visibility into the design itself. Today, 40% of all FPGAs include embedded processors. Most of them are soft cores, but as mainstream embedded processors are added to FPGA devices, this percentage will increase and the complexity of these designs will skyrocket. Modern communications or video applications have an insatiable appetite for performance bandwidth. To deliver this performance, new applications are moving algorithms that previously executed in software to the FPGA hardware. With this change comes a significant verification and debug problem. We have good tools to debug software but when the associated hardware does not work, the system as a whole does not work. In order to debug these new embedded designs with FPGAs, the designer needs the ability to incrementally compile the hardware code along side of the processor in the chip and debug them together.

Given the progress FPGA silicon providers are making in pacing with Moore's Law and coming to market with phenomenal capabilities, it would be a shame to allow design tools and methodologies to slow us down. The EDA industry must meet the challenge. Advancements like giving designers the ability to see how a design behaves in the physical chip (often the actual target FPGA itself) by running it in-system while still having access to all the capabilities and flexibility of a software simulator (like those provided by GateRocket) are great breakthroughs that will help FPGAs make continued in roads in the traditional ASIC market and bring the power of programmability to more companies.

 

The First Honest FPGA Pitch: by Gary Smith

Background
Ok, so maybe I'm exaggerating, but it was certainly the first one I've seen and I've seen a lot. For a little background I was part of the semi-custom, or gate array, community during the 1980s. When FPGAs hit the scene, in the mid 1980s, I took a look at them and easily come up with a formula that divided the gate array market from the FPGA market. It was based on production cost of the die and packaging. There was really not much conflict: FPGAs took up the low gate count end of the market, one that we were happy to relinquish due to low profit. At every node change FPGAs were capable of doing a higher percentage of the design starts, but the volume market was still a gate array, or standard cell ball game.

Towards the late 1980s the FPGA marketing establishment became dissatisfied with their fairly predictable market share and started exaggerating their capabilities. One of the ways they did this was by using what became known as the Paterson Gate. To get a Paterson gate count you took the number of ASIC gates that an FPGA could handle and multiply by four, or six if you were pushing performance. Other exaggerated claims were made and they were made loud enough and often enough to cause confusion in the market place.

In 1989 Stan Baker, of EE Times, put together a panel consisting of the marketing managers of the major FPGA vendors and me. The FPGA guys would give their pitch and then I would point out the exaggerations and sometimes outright lies, to the audience. The panel became popular and Stan shopped it around to most of the conferences. I don't think any of this did anything to move the market share needle, but it was all good fun. Unfortunately I got tagged as being anti-FPGA, which wasn't true.

Moshe takes over as CEO of Xilinx

I've known Moshe for a while now and consider him a good friend. I've always known him to be honest, but even so moving to Xilinx he was bound to be influenced by the Xilinx culture. So I was interested I how he was going to handle his presentation at SNUG. He didn't let me down, and as the title of this note says I heard my first honest FPGA presentation.

The New FPGA Market
Not to take any credit away from Moshe, it was actually not difficult to put and end to the exaggerated marketing claims of the past. The reason is that at 45nm an FPGA had enough gates to do true SoC designs. That has opened up a whole new world to the FPGA designer. Now will that bring and end to the ASIC market as we know it? Of course not and Moshe made a point of saying so. What has happened though is a convergence of enough gates, true globalization of electronic design and the move to ES design and you have the reverse of the perfect storm. Everything has become bright and shiny for the FPGA world. Moshe's move to Xilinx couldn't have come at a better time. His experience in both the ASIC business and the EDA business added to his mature, level headed management style is just what the FPGA world needed to take advantage of this golden opportunity. Xilinx is in for quite a ride.

The FPGA Design/Verification Challenge
This is no free ride for the FPGA designer. All of this capability puts him right into the path of systems design. He will need to take his skill level up another notch and especially with the addition of embedded microprocessors he now needs to design and verify both the hardware and software. His EDA tool needs will increase as will the demand on the EDA vendors to provide out of the box flows. They cannot afford the usual Application Support levels common in today's SoC design. It will be interesting to follow the brave new world of FPGA SoC design.

 

 

 

The founder and Chief Analyst for Gary Smith EDA. Previously, he was the Managing Vice President and Chief Analyst of the Electronic Design Automation Service, Design & Engineering Cluster at Gartner Dataquest.