Posted by Dave Orecchio on Sun, Aug 30, 2009 @ 08:20 PM
GateRocket had a great Design Automation trade show. See our earlier post on the topic. During the conference, Graham Bell of EDA Cafe interviewed the GateRocket CEO. View the interview bu clicking on the picture.
During the interview Dave talked about the two announcements at DAC:
- Shipping of our Stratix IV RocketDrive
- The release of version 4.0 of our software.
The RocketDrive release was expected and the customers who received them benefited by being able to debug their design code on early silicon before their system boards were available in the lab and with an environment where it is much easier to find bugs.
During his discussion of the version 4.0 software he reveled RocketVision's unique ability to pinpoint the root cause of errors and enables the user to run code in or out of the FPGA without rebuilding the chip. A boon for productivity while debugging the FPGA.
Dave also discussed being listed on Gary Smith's "Must See" list, the ability to run up to 8 simultaneous RocketDrives at once for system validation and being the "Only Game In Town" when it comes to FPGA verification and debug.
Graham asked about the key trends we see. Listen to Dave's view on the topic of FPGA design starts and the innovation and fast pace of the FPGA technology offered by the device vendors.
Posted by Dave Orecchio on Mon, Jul 20, 2009 @ 07:11 AM
Today we announced shipment of our brand new RocketDrive for the Altera Stratix IV. We also announced a new version of our debugging software that brings new levels of flexibility to the FPGA Designer and Design Verification engineer. See the release here.
New Stratix IV RocketDrive brings verification capacity to new levels
The new Stratix IV RocketDrive is very exciting since it encloses the largest commercially available FPGA on the market today (Stratix IV GX530 - FPGA board shown above). Those of you who have learned about how a RocketDrive works know why there are two of these monster devices in each RocketDrive.
The GX530has 530,000 logical elements which equates to more than six million ASIC gates (according to FPGA vendor estimates). With this kind of capacity this RocketDrive can serve as a verification platform for all Altera FPGA designs and many ASIC projects as well. With this capacity, we may have hit the tipping point where many ASIC projects can be done in a single FPGA. Clearly the industry analysts think so for the communications market and even more for the Military market.
New FPGA software changes the game
With this release of the Stratix IV RocketDrive comes a new release of our RocketVision software, version 4.0. To understand the benefits of this new FPGA software, you need to look at the key benefits of the tool and GateRocket's philosophy about design tools. Our goal is to deliver verification software that leverages your existing environment without change. We have done that with the previous release. Unique in hardware assisted verification circles is the ability to place a design into hardware and verify it against your existing test bench and tools without change to those tests or tools. We have done just that and more.
Release 4.0 brings with it the ability to perform extensive debug without having to re-build the device! We've added some secret sauce to the solution that eliminates one of the biggest complaints (and productivity drains) of FPGA software and devices, very long FPGA build times.
We give the user the ability to turn on and off visibility within the device and select which blocks to run in the FPGA or the HDL simulator, and we do this without an FPGA recompile. If you want to learn more, please come and see us at the Design Automation Conference next week or register for the webinar titled "what you missed from GateRocket at DAC".
These are exciting times indeed when new innovations like GateRocket's FPGA design tools change the way companies design and debug their FPGA projects.
Posted by Dave Orecchio on Thu, Feb 26, 2009 @ 01:42 PM
Tuesday of this week was Fat Tuesday, the last day of Mardi Gras and it was also the first day of the Design Verification Conference (DVCon) in San Jose, CA.
GateRocket was there with their Mardi Gras beads, demos and more to show the leading design verification engineers the best way to verify and debug the biggest and fattest FPGAs on the planet.
Of course the conference sports the usual ASIC designers, but the majority of the attendees were using FPGAs in their verification process for ASICs or as a central part of their product.
Each of them experienced challenges getting their designs to work in the lab. GateRocket demonstrated the new Device Native verification approach for FPGA verification and debug to packed crowds. They say the conference attendance was down this year but GateRocket was very busy throughout the two exhibition days.
If you missed the action at DVCon and want to learn how to debug a Big Fat FPGA, register for a webinar.
Posted by Dave Orecchio on Sun, Feb 22, 2009 @ 12:41 PM
During these difficult economic times, many companies are getting smaller. For those of us in the electronic industry, only one semiconductor segment is on a growth vector - FPGAs. Growth is coming in the form of new design projects and the devices themselves are growing in capability and capacity - they are mammoth chips. The recent advancement of these devices is good news for companies that are looking for a way to innovate their way out of this economic slump, but the tools used to design and debug them have not kept up.
Late last year, Altera announced the Stratix IV device with over 680K logical elements, the highest density, their highest performance and lowest power FPGA. On February 2nd, the 25th anniversary of Xilinx, they announced the Virtex 6 family of devices with up to 760K logic cells, lower power and faster performance. These two great companies provide the fuel for innovation in a broader set of applications and many more markets, many that were previously the domain of ASIC chips. The next graphic shows this is a very recent change.
Both of these device families sport logic density and performance to satisfy the requirements of most ASIC projects. No wonder why companies have made the shift from ASICs to FPGAs. With these advanced features and without the expensive mask costs, design teams have the opportunity to innovate their next great products on a tremendously powerful programmable canvas.
All of this power does not come without a cost. Design process and tools for these mammoth FPGAs must adhere to the same verification rigor as ASICs else the project will die in the lab bogged down with problems with no clear path to success. The challenge that designers of these chips face is a lack of tools because getting a design to work in an FPGA is different than with an ASIC.
Why not use the same tools as are used for ASICs you ask? Well some are the same, however the process of building a product with an FPGA is different - the design flow introduces new problems that current verification methods don't catch. Since the chips are not custom for a specific application but instead are fixed and programmed for the job, the synthesis and place and route tools must do more and often they do their work in unanticipated ways. The unintended side effect is that they often insert differences in behavior from functional software verification - or the Intellectual Property (IP) block simulation models do not match behavior in silicon. This leaves the designer with no other option - they must see their design working on the chip.
Today, the most prevalent method of seeing the design work in silicon is to use a prototype board or just debug in-system in the lab. Making the shift from the software verification world to the lab removes the flexibility and debugging power of a software simulator. Lab tools are like debugging a vast world through a keyhole! As the chips get bigger, the world is bigger - this approach is not productive - it is a non-starter.
The best solution for this conundrum is to bring the FPGA into the simulator like GateRocket does with the RocketDrive. This solution gives the user unparalleled FPGA verification productivity and as the chips get bigger, so naturally the solution scales.
Let the chips become mammoth, that's more for us to innovate with!