Posted by Dave Orecchio on Mon, Aug 16, 2010 @ 09:05 AM
Embedded processor cores for DSP, microcontroller and microprocessor functions are becoming increasingly common in FPGAs. Both Xilinx and Altera have long offered their own embedded soft IP cores, and a growing trend is to also support the integration of third-party hard IP cores, such as the PowerPC or ARM families. Gartner estimates that approximately 40% of all FPGA designs include embedded processors. The combination of a flexible FPGA platform and a proven, high-performance core saves designers time and effort. And the FPGA suppliers are making it even more efficient through offerings such as Xilinx’ Extensible Processing Platform for the ARM Cortex-A9, which makes customizing the FPGA device for specific function or design requirements easier.
But with the addition of larger and more complex embedded processors, combined with the complexity of the overall leading-edge FPGA architectures, designers are faced with unprecedented verification challenges. A ‘fully loaded’ FPGA with multiple embedded cores and millions of logic cells can literally bring a traditional simulation approach to its knees. Just the density of these devices alone is daunting. But consider that there is also a need to execute and verify software along with the hardware, and designers are looking at multi-million cycle simulation challenges.
GateRocket’s Device Native approach addresses head on the simulation challenges of designing FPGA with embedded cores. With a Device Native approach, which is enabled by our RocketDrive tool, the design team can connect the actual processor in the target FPGA into a simulation environment, significantly accelerating the verification process. The processor in the FPGA can operate in the simulator environment. Meanwhile the design team can focus on behavioral tests of the circuit blocks designed by the team and those purchased as third-party IP. The design team can move forward without a major simulation bottleneck.
While simulation performance is a major challenge in these large, embedded-core-based FPGAs, the RocketDrive offer more than just verification throughput benefits. With it, designers can simulate their designs with silicon-level accuracy and identify problems that typically go undetected until system-level debugging in the lab. In this way they can also spot problems early in the design cycle when they are much easier to find and fix.
We’ll be talking about how this Device Native approach can help designers using embedded processors at next month’s Embedded System Conference in Boston. On Wednesday, September 22 we’ll be leading a technical session beginning at 3:15PM in Room 103 that examines the challenges of debugging and verifying complex FPGAs. The session will provide an in-depth overview of our solution, featuring the RocketDrive and RocketVision verification and debug tools that have proven to significantly reduce the time and effort involved in bringing up working FPGAs, whether for use in production systems or as ASIC prototyping platforms.
Posted by Dave Orecchio on Sun, Aug 30, 2009 @ 08:20 PM
GateRocket had a great Design Automation trade show. See our earlier post on the topic. During the conference, Graham Bell of EDA Cafe interviewed the GateRocket CEO. View the interview bu clicking on the picture.
During the interview Dave talked about the two announcements at DAC:
- Shipping of our Stratix IV RocketDrive
- The release of version 4.0 of our software.
The RocketDrive release was expected and the customers who received them benefited by being able to debug their design code on early silicon before their system boards were available in the lab and with an environment where it is much easier to find bugs.
During his discussion of the version 4.0 software he reveled RocketVision's unique ability to pinpoint the root cause of errors and enables the user to run code in or out of the FPGA without rebuilding the chip. A boon for productivity while debugging the FPGA.
Dave also discussed being listed on Gary Smith's "Must See" list, the ability to run up to 8 simultaneous RocketDrives at once for system validation and being the "Only Game In Town" when it comes to FPGA verification and debug.
Graham asked about the key trends we see. Listen to Dave's view on the topic of FPGA design starts and the innovation and fast pace of the FPGA technology offered by the device vendors.
Posted by Dave Orecchio on Thu, Feb 26, 2009 @ 01:42 PM
Tuesday of this week was Fat Tuesday, the last day of Mardi Gras and it was also the first day of the Design Verification Conference (DVCon) in San Jose, CA.
GateRocket was there with their Mardi Gras beads, demos and more to show the leading design verification engineers the best way to verify and debug the biggest and fattest FPGAs on the planet.
Of course the conference sports the usual ASIC designers, but the majority of the attendees were using FPGAs in their verification process for ASICs or as a central part of their product.
Each of them experienced challenges getting their designs to work in the lab. GateRocket demonstrated the new Device Native verification approach for FPGA verification and debug to packed crowds. They say the conference attendance was down this year but GateRocket was very busy throughout the two exhibition days.
If you missed the action at DVCon and want to learn how to debug a Big Fat FPGA, register for a webinar.
Posted by Dave Orecchio on Sat, Jun 16, 2007 @ 09:16 PM
I am sure that you have heard about Rip Van Winkle, the Dutch villager living in America who, trying to escape his nagging wife by wandering into the forest with his dog and rifle. After drinking elves brew, he falls asleep for 20 years. Years ago, the design automation industry had similarly fallen asleep regarding the move to FPGA devices, see my earlier post about the designers marching to FPGAs. Well, at this years Design Automation Conference, if by only judging by the attention paid to GateRocket, the industry and analysts have awoken to the needs of the FPGA design engineer.
In a recent EETimes article, Altera's CEO John Daane highlights his focus on stealing ASIC market share as a method of growing his FPGA business. He is expecting double digit growth fueled partially by their Hard Copy product, where they take a design that was implemented and debugged for a Stratix II device and make a lower cost, lower power equivalent device. The idea is that their customer would use the programmability of the FPGA to get to market faster and cost reduce if necessary with Hard Copy. This strategy is helped along by the crushing cost of ASIC NREs. Xilinx has a similar technology they call EasyPath. So, not only are the FPGA devices taking share from the ASIC market but the FPGA vendors are aggressively attacking the market with HardCopy and EasyPath. As they succeed, the ASIC design starts, already below 3000 per year will continue their precipitous decline.
If the GateRocket success at DAC is a leading indicator of the market waking up to FPGAs then the FPGA designers will be getting a whole lot of attention in the coming years.
Posted by Dave Orecchio on Mon, May 14, 2007 @ 09:06 PM
It is common knowledge that design verification consumes approximately 50% of electronic design project time and therefore takes center stage at the electronic design premier event, the 44th annual Design Automation Conference. I recently received the following letter from the general chair of DAC, Steven P. Levitan of the University of Pittsburgh, ECE Department where he speaks of the importance of verification.
DAC: Verification Continues to Dominate Program
Steven P. Levitan, General Chair, 44th Design Automation Conference
Verification once again takes center stage as Design Automation Conference (DAC) heads into San Diego next month. This year's program covers a broad range of verification and test topics. You'll find 26 papers, panels, lunchtime discussions and a tutorial covering all forms of verification designed to offer you the latest information and breakthroughs from leading experts.
Speaking of breakthroughs, we offer a warm welcome to GateRocket, a first-time DAC exhibitor who's using the conference to introduce itself and the innovative Device Native verification solution for advanced FPGAs to the designer community. GateRocket joins a lively Exhibition and Suite area with close to 250 of the leading and emerging EDA, silicon and IP providers. Don't miss the opportunity to meet the GateRocket team in Booth #2559.
Allow me to boast a bit more about the conference, starting with three keynotes offering a diverse look at the field of design, verification and test. Oh-Hyun Kwon, Ph.D., president of the System LSI Division of Samsung Semiconductor Business, will offer, "A Perspective of the Future Semiconductor Industry: Challenges and Solutions," during Tuesday's opening session. Lawrence D. Burns, Ph.D., vice president of R&D and Strategic Planning for General Motors Corp., will discuss "Designing a New Automotive DNA" Monday to highlight our Automotive theme. And, Thursday's by Dr. Jan M. Rabaey, the Donald O. Pederson Distinguished Professor in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley, will be "Design without Borders -- A Tribute to the Legacy of A. Richard Newton."
I'm also excited about our day-long seminar for management teams worldwide to be held on Tuesday. One of the world's experts on innovation management -- Geoffrey Moore, author of "Crossing the Chasm" -- will join technologists Raul Camposano and Jim Smith to present a tutorial on innovation.
We look forward to seeing you in San Diego! Don't hesitate to approach me or any of the other DAC Executive Committee members during the conference to give us your impressions. Your feedback is important.
More details about DAC are available at: http://www.dac.com/.