RocketBlog - a discussion about all things related to FPGA verification and debug

DAC Panel: Specialized FPGA tools needed to keep up with size and complexity

ANAHEIM, Calif. - A Pavilion Panel at DAC, entitled "Is the FPGA Tool Opportunity an Oasis or Mirage?" raised the question about the need for more specialized and sophisticated tools for FPGA design. The answer from the panelists was a resounding "yes".

The panel was smoothly moderated by FPGA Journal editor Kevin Morris and brought together a trio of experienced FPGA tool experts - representatives from Mentor Graphics (Simon Bloch), Synopsys (Andrew Dauman) and US Venture Partners (Jacques Benkoski). There was universal agreement that given the complexity of modern FPGAs, design tools must keep pace, especially in areas such as verification and synthesis.

The panelist acknowledged that the tools offered by the FPGA vendors themselves served users well for the first several generations of FPGA devices, but with those same silicon providers significantly improving their devices with each new generation, tool performance and efficiency needs a boost. They debated whether those tools should continue to come from the FPGA vendors themselves and again there was agreement that the likes of Xilinx and Altera need to focus on their core competence of the underlying ‘platform' or fabric of their devices, and that there was an opportunity for specialized tool suppliers to help address the growing challenges in the design flow for FPGAs.

The panel likened the current state of FPGA to the adolescent days of the ASIC industry when the first suppliers of those custom devices also offered their own tools, often for free. But as ASIC complexity and size increased, it became clear that more advanced tools were needed and this played a large role in the evolution of the modern EDA industry.

Similarly, the days of FPGA designers relying on free tools are numbered, especially at the high end of the market. "Free is a four-letter word that begins with F," joked USVP's Benkoski, emphasizing that, in the end, a free tool may be more costly to a design team or company if it causes longer design cycles or can't handle the complexity of a design.

The EDA suppliers agreed, noting that a commercial tool will almost always be a wiser investment for a high-end design project considering the breadth of use and testing it gets across multiple customers, and the fact that supporting an in-house tool is an overlooked cost and headache that many companies overlook.

At GateRocket we agree with this sentiment, having seen first hand the need for more powerful verification and more efficient debugging capabilities by FPGA designers. Our exclusive focus on FPGA verification and debug allows us to hone in on the specific issues FPGA designers face (remember our founder was an FPGA designer himself!) and develop solutions that are optimized for the unique requirements of today's most advanced FPGA devices.

Live from DAC 2010: Gary Smith on What's Hot

ANAHEIM, CAlif. - One of the highlights of the Design Automation Conference every year is Gary's Smith "What's Hot" list. He spends the year trolling through EDA vendors' pitches, both large and small companies, to find the most interesting new technology available for chip designers. A daunting task considering the number of new start-ups emerging all the time, not to mention the large EDA vendors that continue to come out with add-on products.

But Gary carries on, and always comes up with a pretty complete and compelling list of things to see. He breaks the new innovations down into logical categories - physical design, verification, DFM, etc. etc. He even produces a wall chart that displays all the different types of EDA tools and technologies available, and all the EDA vendors who provide tools in each bucket.

GateRocket was pleased to be included in Gary's very exclusive list of "Must See" new technologies at this year's DAC. Gary presented his list last night at a special welcome reception hosted by EDAC, and then again this morning on the DAC show floor. Both presentations drew large crowds of designers, anxious to see what's new and exciting this year.

Gary spent a bit of time talking about how GateRocket has evolved from being an emulation/hardware company, to offering a complete debug and verification solution that consists of the RocketDrive hardware as well as the newly enhanced RocketVision software debug environment. He highlighted the new SoftPatch features in the new release 5.0. And, he stressed the criticality of enhanced verification and debug for FPGAs in general.

We're glad Gary is on board with what we see as a growing crisis in FPGA design, and we thank him for including GateRocket in his prestigious list.

Is FPGA's progress threatening to undermine programmability's greatest benefit?

 {The following is an excerpt from a blog post by noted industry veteran Jim Hogan. The full version of the blog is on the System Level Design site.}

Gary Smith, the noted EDA industry analyst, wrote an interesting blog post recently. In that blog, he spoke about the progress the FPGA suppliers have made in adopting new processes, thus offering a more robust design platform. In fact, new product families such as the Virtex-6 from Xilinx are taking market share from traditional ASIC design starts and becoming a more viable end-product alternative. There are many reasons for this. One of the most significant is the cost of delivering a leading edge ASIC. If FPGAs can meet the market requirements in terms of cost, performance and power, they are a great alternative to the ASIC without the silicon risk.
Their capacity, performance and even lower costs have made more than a few companies think seriously about leveraging the benefits of programmability in a more widespread way and not just looking at FPGAs as prototyping platforms.

But Gary sounds a note of caution by saying, "There is no free ride for the FPGA designer." It is true that by upping the ante on the capabilities of their FPGA devices, the silicon suppliers have thrown down the gauntlet from a design standpoint. New methodologies and tools - true system-level approaches like we have seen for hardwired gate arrays - will be required. Gone are the days of the free FPGA tools from Xilinx and Altera doing the job.

As with most areas of design automation, verification has become the major bottleneck. For FPGAs it comes down to two issues, performance and efficiency of visibility into the design itself. Today, 40% of all FPGAs include embedded processors. Most of them are soft cores, but as mainstream embedded processors are added to FPGA devices, this percentage will increase and the complexity of these designs will skyrocket. Modern communications or video applications have an insatiable appetite for performance bandwidth. To deliver this performance, new applications are moving algorithms that previously executed in software to the FPGA hardware. With this change comes a significant verification and debug problem. We have good tools to debug software but when the associated hardware does not work, the system as a whole does not work. In order to debug these new embedded designs with FPGAs, the designer needs the ability to incrementally compile the hardware code along side of the processor in the chip and debug them together.

Given the progress FPGA silicon providers are making in pacing with Moore's Law and coming to market with phenomenal capabilities, it would be a shame to allow design tools and methodologies to slow us down. The EDA industry must meet the challenge. Advancements like giving designers the ability to see how a design behaves in the physical chip (often the actual target FPGA itself) by running it in-system while still having access to all the capabilities and flexibility of a software simulator (like those provided by GateRocket) are great breakthroughs that will help FPGAs make continued in roads in the traditional ASIC market and bring the power of programmability to more companies.