Posted by Dave Orecchio on Mon, Jul 20, 2009 @ 07:11 AM
Today we announced shipment of our brand new RocketDrive for the Altera Stratix IV. We also announced a new version of our debugging software that brings new levels of flexibility to the FPGA Designer and Design Verification engineer. See the release here.
New Stratix IV RocketDrive brings verification capacity to new levels
The new Stratix IV RocketDrive is very exciting since it encloses the largest commercially available FPGA on the market today (Stratix IV GX530 - FPGA board shown above). Those of you who have learned about how a RocketDrive works know why there are two of these monster devices in each RocketDrive.
The GX530has 530,000 logical elements which equates to more than six million ASIC gates (according to FPGA vendor estimates). With this kind of capacity this RocketDrive can serve as a verification platform for all Altera FPGA designs and many ASIC projects as well. With this capacity, we may have hit the tipping point where many ASIC projects can be done in a single FPGA. Clearly the industry analysts think so for the communications market and even more for the Military market.
New FPGA software changes the game
With this release of the Stratix IV RocketDrive comes a new release of our RocketVision software, version 4.0. To understand the benefits of this new FPGA software, you need to look at the key benefits of the tool and GateRocket's philosophy about design tools. Our goal is to deliver verification software that leverages your existing environment without change. We have done that with the previous release. Unique in hardware assisted verification circles is the ability to place a design into hardware and verify it against your existing test bench and tools without change to those tests or tools. We have done just that and more.
Release 4.0 brings with it the ability to perform extensive debug without having to re-build the device! We've added some secret sauce to the solution that eliminates one of the biggest complaints (and productivity drains) of FPGA software and devices, very long FPGA build times.
We give the user the ability to turn on and off visibility within the device and select which blocks to run in the FPGA or the HDL simulator, and we do this without an FPGA recompile. If you want to learn more, please come and see us at the Design Automation Conference next week or register for the webinar titled "what you missed from GateRocket at DAC".
These are exciting times indeed when new innovations like GateRocket's FPGA design tools change the way companies design and debug their FPGA projects.