RocketBlog - a discussion about all things related to FPGA verification and debug

Survey Says: FPGA designers at or near a debug crisis

 

A lot of you have told us you're in pain. Enough that we began to ask ourselves whether there are bigger debug problems brewing in FPGA design. To answer the question we turned to our friends at The FPGA Journal. They helped us put together a survey to ask FPGA designers what causes them pain in the FPGA design process. FPGA designers - that's you - responded en mass and for the first time we have a picture of the biggest problem facing FPGA designers.  

Designers are in Crisis

Nearly one quarter of FPGA designers today are in crisis mode when it comes to the amount of time spent (wasted) debugging designs. Current design practices, specifically the process for identifying and fixing bugs in FPGAs by looping from the lab, where a bug is identified, back through simulation, synthesis and place and route, adds between 92 and 148 days to the typical FPGA design process. These times are growing fast as design and chip complexity increases threatening one of the primary advantages of FPGA technology - rapid time to market.  

Fix Bugs Up Front

By contrast, if FPGA design bugs can be identified and fixed up front in the design process, the survey respondents told us it takes an average of 55% less time to find and fix a bug.  The problem is that many of the bugs only manifest themselves in the programmed FPGA.  Therefore, in order to expose the bug and correct it up-front in the design process, the FPGA device must be integrated into the simulation environment in a way that combines software-like flexibility with the implementation accuracy of the FPGA – like is only done with a RocketDrive and RocketVision.   

Long Synthesis-Place-Rout Cycles are the Problem

Users identified long synthesis-place-route cycles as the key productivity issue.  Using a hardware-in-the-loop solution that links simulation with the FPGA and enables debug without rebuilding the device with each debug iteration addresses the problem.  This is a significant improvement to the present methodology (looping through simulation-synthesis-P&R and debugging in the lab). Imagine cutting design time in half by eliminating unnecessary cycles of synthesis and place-and-route, which survey respondents identified as the most acute time consumers. 

Cut Time-to-Market by 60 days

The good news is this: Time to market can be reduced by more than 60 days for large, complex FPGAs by making a simple change in the design process! The GateRocket RocketDrive enables this paradigm shift in the FPGA design process. This solution further reduces the time it takes to find and fix real hardware bugs in simulation because it accelerates simulation at the same time and further enables the flexibility to run rapid test and verification cycles in the design running in the target hardware with the simulator.FPGA Journal editor Kevin Morris describes it as "the best of both worlds...the visibility, control, flexibility, and iteration time of the (software) simulator combined with the raw speed of native FPGA hardware."

If you would like to learn more, please contact us.

You’ve got debug questions? Ask the Rocket Scientist!

Throughout our web site and in particular this blog, we make some pretty impressive claims about how GateRocket's innovative solutions can save you time and effort in verifying and debugging complex FPGA designs. Our tools have been proven by some of the world's leading designers to do all the great things we claim. And, thanks to a recent survey we have conducted, we're sure we are attacking a problem that's becoming an increasingly painful one for a lot of you, too.

But we know everyone has unique needs and one size does not fit all. Sometimes you need the advice of an expert and we have just the guy. Meet Dr. Seymour Gates. He's our resident Rocket Scientist - a vastly experienced and capable advisor on all things related to FPGAs, especially how to verify and track down tricky bugs as these devices become more complex. Normally, he spends his day working away in his lab, dreaming up new ways to make life easier for FPGA designers. But now, he's available to you, through our RocketBlog, to offer up suggestions and insider advice that will help you get rid of pesky intruders in your RTL code, track down hard-to-find pests in your simulation results, and stop the synthesis-to-place-and-route runaround these unwanted interlopers cause.

From time to time, we'll post your questions and let the Dr. Gates go at them with his ample tool box of tips and tricks. Your queries can be specific to a particular design you are working on, or just general questions about how our RocketDrive and RocketVision products work.

So if you are working on a tough FPGA problem, or just want to understand how GateRocket's products can help improve the efficiency of your FPGA design process, send us a question and we're sure our resident Rocket Scientist will help you out.

Here's our first one on using GateRocket to help verify and debug a design with DDR memory:

Dear Dr. Gates:
I have a commercial board with an FPGA and DDR memory, and I want to simulate and debug my design which contains my custom logic and an IP core for the DDR interface. Can the GateRocket handle this and the DDR memory? What would be the advantage of using GateRocket over just compiling my design and executing the design on the board that I have?

Dr. Gates responds:
Using the GateRocket system the FPGA side of the DDR interface would be loaded into the RocketDrive and tested in the FPGA hardware. The DDR memory simulation model would stay in the simulator and you can debug the rest of the design separately. We can handle the Xilinx and Altera standard IP blocks from the Mega Block Wizard (Altera) or Core Generator & MIG tool (Xilinx), as well as the larger interface blocks.  

Having the acutal FPGA device integrated into your simulation environment has limitless possibilities.  The customers that I have been consulting with have been finding new ways to use this technology, perhaps you will too.  

If you have a question for Dr. Seymour Gates, please provide your question by filling out the form on this page.

The "Ah Ha" Moment - GateRocket is an FPGA design platform

A few weeks ago, we introduced the newest version of our RocketVision® software, version 5.0, which includes a feature we call SoftPatch. Essentially, SoftPatch enables designers to patch their FPGA hardware with an edited RTL software block and see the effect on the chip's operation- without re-building the FPGA. We do this by allowing the user to select any number of individual design blocks to have the flexibility to run in their simulator or execute in the FPGA that is inside GateRocket's RocketDrive® hardware verification system. The user can then decide at simulation time which blocks execute inside the FPGA or in the simulator. This powerful capability enables them to select a block, instruct it to run in the simulator and then make changes to the RTL of that block and simulate it in software while the rest of the design executes in the native FPGA hardware in the RocketDrive. The user can repeat that sequence for as many blocks as they choose, again at runtime without rebuilding the FPGA device.

Quantifying the benefit of SoftPatch
This lets them find and fix bugs faster, and avoid unnecessary re-runs of time-consuming synthesis-to-place-and-route iterations. In early customer engagements, we have seen this reduce overall design bring-up time by up to 50% or more compared to traditional approaches. What's more, we have seen examples where companies who are designing large FPGAs are experiencing 18 hour synthesis-place-route times and are doing anywhere between 100 to 200 iterations for a given project. Taking the average number of iterations, this means they are spending 2,700 hours building the FPGA, or 112, 24 hour days or 22.5 weeks. By cutting this time in half they could save 11.25 weeks or more of project time. Not counting the cost of a time-to-market delay, that amounts to $32.5K per employee that is non productive during that period.

While we were talking to the press, market analysts and customers about this new feature, we literally saw them having an ‘ah ha' moment about GateRocket. The prevailing perception of our company was that we are a hardware verification supplier - mainly because we always talked about how much faster your FPGA verification can run with our RocketDrive hardware product. That's still true, but what people didn't realize is that, with RocketVision, we offer a very efficient and flexible FPGA design platform, too.

SoftPatch enables design optimization
And not only does our system allow designers to correctly locate, isolate and correct a bug - i.e. fix what is broken - it also allows them to optimize their design and perform a ‘what if' analysis based on different constraints or requirements they might have. Our system lets designers find opportunities for optimization and verify that they will work in a very short-loop way. For example, you have a design in the field and your boss asks you to enhance an algorithm. You take the design, select the blocks that you may have to change to be patchable, and while your design is running in hardware, you patch the blocks you want to change to enhance the algorithm with the flexibility and iterative benefits of your software environment. So not only are we helping make designs work the way they are supposed to, we are helping find way to improve an algorithm or add new functionality altogether.

Key benefits of flexibility to execute blocks in hardware or simulate in software
A key advantage to this approach is that the original design intent is consistently preserved throughout the process and across the design domains RTL-gate-silicon in the FPGA. Bug fixes and optimizations can be done in a very interactive and integrated way, eliminating the need for complete re-spins and re-verification runs. Because RocketVision works with existing simulation environments from the top three EDA vendors, as well as being tightly integrated with RocketDrive, the ease and efficiency of use is an order of magnitude better than other hardware-in-the-loop verification approaches, a significant benefit that reduces time and risk for development projects.

Look for more innovation from GateRocket
As we continue to develop the software side of our solution, we believe our customers will guide us to innovate even more ways to enhance the design capabilities this solution offers. With the complexity and time to market challenges product developers are facing, more efficient design methods are required. Our vision is to build from our foundation of strength in verification and debug, and bring more value to the overall design process as well.