Debugging FPGA designs may be harder than you expect
Posted by Dave Orecchio on Fri, Oct 30, 2009 @ 01:03 PM
EDN published technical article by GateRocket's founder Chris Schalick about FPGA debug.
Please read the article here.
Of course, the purpose of these articles is to discuss technical challenges and general approach to the solution without being commercially motivated. Chris has done that in his article and you can read about the challenges by reading his paper on EDN.
If you are looking for a solution, here is the rest of the story:
So, what's the solution to the FPGA debug challenge?
After battling his way through similar problems, Chris came to the conclusion that a different approach was required. Designers needed an environment where software and hardware representations could co-exist: where each functional block could reside in the software domain, or in the hardware realm, or in both.
Suppose you could move the gate-level representations of any known-good blocks (i.e. some trusted IP cores) into the same type of FPGA you are targeting for your real-world design? Suppose that you could now verify these blocks in conjunction with the rest of the design running in your software simulator of choice? Right-from the start, your verification time would speed up.
After each block is verified at the RTL (or behavioral) level, its synthesized equivalent can be moved over into the physical FPGA. If issues arise, the RTL verification can be compared with the version in the physical FPGA. By means of a special software application, the signals from the peripheries of these blocks (along with any designated signals internal to the blocks) could also be compared on-the-fly.
This flexible solution is available now from GateRocket, in the form of the RocketDrive. The RocketDrive houses your target FPGA in removable caddy that plugs into a standard 5¼" drive bay in a standard workstation (figure below). RocketDrives come in a variety of models, each targeted toward a different family of FPGAs from Altera or Xilinx. In each case, the RocketDrive contains the largest member of the family with which you are working.
Each RocketDrive contains the largest member of the FPGA family with which you are working.
With the RocketDrive, designers start with software simulation. Then using an interface, the designer can place all proven blocks into the drive, while keeping blocks under development in the simulator. This accelerates simulation right away. As new blocks are finished they can be moved into hardware, for “device native” verification and acceleration.
Unlike a simulator, all of the parameters associated with the design's I/O pins are verified in a physical FPGA, and unlike a development board, your design does not need to be modified in any way in order to use this technology. GateRocket’s software suite provides advanced debug and visualization for a workhorse solution that drops into your design environment without any disruption to your flow. Both hardware and software complement industry-leading simulators from Cadence, Mentor and Synopsys. In fact, the debug and visualization features are enabled and controlled from within the user's software simulator, which means there is no methodology change.
Now designers can test behavior in a physical chip, running just as it would in-system, while accessing all the capabilities and flexibility of their software simulator. It allows engineers to quickly detect, identify, and correct differences between the RTL and the physical chip. Results have been repeatedly validated by our customers, who accelerate verification by a factor of up to 10X or more, while reducing the in-silicon debugging process by a 30X.
FPGA debugging harder than you think? It’s time to get creative about how we use our chips!