FPGA Debug, you can't fix what you can't see
Posted by Dave Orecchio on Wed, Jan 20, 2010 @ 02:04 PM
The legendary baseball pitcher Walter "Big Train" Johnson once said, "You can't hit what you can't see," referring to his blinding fast fastball that helped put him in the Hall of Fame. We're pretty sure the Big Train never had to deal with designing big complex FPGAs, but his words of wisdom apply. Here's why:
Designers struggle with traditional FPGA verification methods, particularly as they move from RTL through the typical synthesis-to-P&R process. Not being able to observe the entire design is a main culprit in what can be a seemingly never-ending design loop. Everything looks great after you run an initial RTL simulation, but lo and behold - after you synthesize to your FPGA target and load the results, there are errors you didn't see in the first go-round. Where did they come from?
You re-check your RTL and simulation. Both are correct. You add some debugging logic around what you think may be the problem. Wait for synthesis and routing to complete. #$@%@%!!! Still doesn't work!
But you can't see any problem with your RTL or simulation, no matter how hard you look, and you can't get it to work how many tweaks you try. The result is big delays and big frustration.
Turns out, synthesis has thrown you a curveball. See, your simulation runs ignore the synthesis pragmas - those directives that give synthesis tools the flexibility to fit your design into silicon. Your RTL simulation doesn't match your netlist and your FPGA design is overwriting registers that you didn't care about in your RTL.
But in your view of the world, you can't see that from just your usual methodology: every step in your process seems to produce the result you expect - except for the finished FPGA. Simulation was fine. Synthesis and routing complete with no errors. The netlist loads without issues. But the design doesn't work.
That's where GateRocket gives you a fighting chance, an opportunity to "see the un-seeable." Our RocketDrive bridges the gap between RTL and the FPGA by putting the FPGA into your simulator and giving you the tools you need to move back and forth between RTL and the FPGA without guessing, re-synthesizing and re-routing. Finding RTL code that does not implement the way it simulates becomes simple with RocketDrive and doesn't require long loops through synthesis and place & route each time you want to examine and debug different parts of the design.
So if you want to play in the big leagues of FPGAs, you better arm yourself with the right equipment. Even the Big Train could understand that.