RocketBlog - a discussion about all things related to FPGA verification and debug

Survey on FPGA debug and verification: Tell us where the pain is

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We know modern, complex FPGAs introduce a host of new challenges into the design process. At GateRocket we are always trying to understand where our customers are feeling the most pain in how you develop FPGAs, particularly in the debug and verification stages.

As we continue to enhance and refine our offering, it's helpful to hear first hand from FPGA designers where the specific pain points are. Where are you spending the most time? Which steps are especially onerous as designs get bigger and full of more IP blocks? Which tools are slowing you down the most? What can we do to help?

We have put together a brief survey - no more than 10 minutes - to help us characterize current FPGA design issues and understand where the most time is being consumed - and thus impacting your overall product development schedules.

The survey has now closed.  Thanks for everyone who shared your opinions. We will publish the general findings soon so you can understand how your challenges stack up to your peers in the FPGA design world.  In the meantime, congratulations to the people from the following companies won the Amazon gift certificate:

• Naval Undersea Warfare Center
• Mitre
• Cisco
• Tellabs
• Starent Networks
• BroadcastPix