FPGA Survey Highlights Debug Crisis
Posted by Dave Orecchio on Mon, Jul 26, 2010 @ 04:10 PM
The popular web site and newsletter FPGA Journal conducted a survey of its readership in the spring of 2010 to determine the biggest issues in verifying and debugging complex FPGAs today. Over 300 FPGA designers and managers responded to the survey, citing the bottlenecks they face as they try to bring up today's most advanced FPGAs.
The survey produced some eye opening results, particularly among the segment of the survey population doing complex FPGA design. On average, the number of iterations required to bring up a working FPGA is more than 100, a situation unheard of in previous eras of FPGA use, and one that is threatening the biggest FPGAs to being with – faster time to market and/or rapid prototyping.
The survey revealed that the number one issue causing lengthy debug times is tracking down errors in RTL code. This can be a result of designer error, or, increasingly, because of issues related to other design tools such as synthesis and place and route, or IP cores. Regardless of the source, these types of errors are tougher and tougher to find using traditional FPGA debug and verification techniques.
In fact, the survey results show that debugging a complex FPGA can now represent to 92 days of the overall development cycle!
If you are having issues with FPGA debug and verification, you are not alone. Of course, we believe GateRocket can help address this growing crisis with our solutions for giving designer increased visibility into their FPGA design through our unique Device Native approach.
To see for yourself what other designers are experiencing, go here to sign up for a 7-page summary of the survey results