Hard Times for FPGA Designers
Posted by Dave Orecchio on Sun, Apr 01, 2007 @ 08:59 PM
It's not easy to design an FPGA nowadays. Designs are getting larger according to a survey conducted by EE Times. The complexity of FPGA designs has escalated, the tools that this class of design engineers has at their disposal is insufficient. I guess you could say that these are hard times for FPGA designers.
Many design teams are applying the same tools and methodologies that they previously used for ASIC design for their new FPGA creations. This trend is more numerous as designers march toward FPGAs. In the US, the average gate count for an FPGA design is 2.4 million gates, increasing to more than 4 million gates by 2008.
Even with sophisticated tools, FPGA designers suffer from the same long verification cycles as their ASIC brethren. The EE Times survey further elaborates functional verification, getting the design to work on the printed circuit board and timing closure as the top three problems.
Using a rigorous verification methodology is not enough. Traditional simulation tools help shake out the intent of the design but can't anticipate the unintended effects of placing that design onto the FPGA device. This is especially true where third party IP is used. Indeed, with 2+ million gate designs, more than one third of each design is comprised of reusable IP. We see this with every customer, and I can't recall when a design did not use FPGA vendor and third party IP.
FPGA complexity and speed are increasing with every passing day. With the right tools, the FPGA designer can apply their art to creating great products and break the cycle of hard times.