What FPGA Verification Problem?
Posted by Dave Orecchio on Mon, Sep 24, 2007 @ 09:28 PM
We have been discussing design verification of large FPGA devices for some time. As an evangelist for the industry, it is great to see industry leaders come out and acknowledge the problem and propose any solution (current or future) to it. The recent press release by Xilinx is a validation of the need for an innovative solution to the large FPGA device verification problem.
On August 14th, Xilinx made an announcement on the topic. They issued a joint press release with Cadence, Mentor Graphics and Synopsis to tackle Ultra High-Capacity FPGA Design Verification. This is good news for FPGA designers. The problem is caused by the size and complexity of modern day FPGAs, please see my earlier post on the topic. As these devices become more and more complex, software simulation alone is not a scalable solution. As FPGA silicon geometries scale, so does the verification challenge and no software simulation-only solution can keep pace.
GateRocket applies an innovated approach to the problem by combining the actual FPGA with the software simulator, an approach they call Device Native Verification for FPGAs. By using the FPGA device in verification , the solution scales with whatever complexity the new deep sub-micron devices can deliver.
Let's keep our heads out of the sand and leverage solutions like the one from GateRocket so we can benefit from the great capabilities these new FPGA devices have to offer!