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Device Native Verification Defined

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There are several established approaches for FPGA verification and validation and they generally fall into two categories.  These approaches are inadequate for debugging modern advanced FPGA designs therefore a new approach is urgently needed.  Let's review these current methods and discuss a new, more productive and accurate approach that is called Device Native verification. 

The first approach uses tools (Simulators) that help the engineer debug the hardware design modeled in Verilog or VHDL Hardware Description Languages (HDL).  These tools either provide better methods for viewing design behavior through simulation waveforms and work with the Test Bench (a test program) to ensure the design is exhaustively tested.  The second uses tools that are inserted into the FPGA design so that the user has internal visibility into the design when it is in the lab during design bring-up. 

Current FPGA Verification and Validate Approaches:

1. Simulation based tools are very powerful and flexible but since they operate on models of the design (which are abstracted away from the behavior of the actual silicon) the verification is only as good as the models themselves.  Once more, they are blind to errors that are injected into the design by down-stream synthesis and place and route tools or Intellectual Property (IP) blocks where the physical block is inserted at the place and route step. 
2. Tools that are inserted into the design in-system to view device behavior suffer from different significant limitations.  The user is limited by the number of signals inside the chip that are visible. They are also constrained by what they can see since these tools use precious on-chip resources and what they see is a translated version (gate-level) of the original HDL design so the engineer has difficulty relating the results with the original design intent.  Additionally, as a debug vehicle the engineer is constrained by the testing that can be performed since the device can only be stimulated by the signals in the system making it difficult to test those difficult to create corner cases. 

New Device Native Verification Approach: 

As FPGA devices become more complex, designers search for new, more productive and effective approaches.  The ideal solution would be one that merges the best of both worlds by providing the Native FPGA Device behavior while being controlled by the simulation testing environment with all of the richness of software debugging tools.  The good news is that there is a solution that has these characteristics and GateRocket calls this Device Native verification for FPGAs. 

Device Native verification characteristics:

• Provides exact FPGA device behavior in the software simulator
• Enables use without changes to the FPGA design source tree
• Can be used productively without a long and difficult start-up process
• Does not change the methodology of existing design verification methods and tools
• Enables advanced debugging features that deliver direct detection and diagnosis of in-silicon bugs
• Eliminates the need for slow and complex models of advanced intellectual property components

If you experience dead FPGA designs in the lab, slow simulation times or difficulty using or evaluating purchased intellectual property blocks, then consider learning more about Device Native verification.  GateRocket created this new category of design tool specifically targeted to FPGA verification and debug. 

Learn more by attending one of our events.