Mammoth FPGAs Require New Tools
Posted by Dave Orecchio on Sun, Feb 22, 2009 @ 12:41 PM
During these difficult economic times, many companies are getting smaller. For those of us in the electronic industry, only one semiconductor segment is on a growth vector - FPGAs. Growth is coming in the form of new design projects and the devices themselves are growing in capability and capacity - they are mammoth chips. The recent advancement of these devices is good news for companies that are looking for a way to innovate their way out of this economic slump, but the tools used to design and debug them have not kept up.
Late last year, Altera announced the Stratix IV device with over 680K logical elements, the highest density, their highest performance and lowest power FPGA. On February 2nd, the 25th anniversary of Xilinx, they announced the Virtex 6 family of devices with up to 760K logic cells, lower power and faster performance. These two great companies provide the fuel for innovation in a broader set of applications and many more markets, many that were previously the domain of ASIC chips. The next graphic shows this is a very recent change.
Both of these device families sport logic density and performance to satisfy the requirements of most ASIC projects. No wonder why companies have made the shift from ASICs to FPGAs. With these advanced features and without the expensive mask costs, design teams have the opportunity to innovate their next great products on a tremendously powerful programmable canvas.
All of this power does not come without a cost. Design process and tools for these mammoth FPGAs must adhere to the same verification rigor as ASICs else the project will die in the lab bogged down with problems with no clear path to success. The challenge that designers of these chips face is a lack of tools because getting a design to work in an FPGA is different than with an ASIC.
Why not use the same tools as are used for ASICs you ask? Well some are the same, however the process of building a product with an FPGA is different - the design flow introduces new problems that current verification methods don't catch. Since the chips are not custom for a specific application but instead are fixed and programmed for the job, the synthesis and place and route tools must do more and often they do their work in unanticipated ways. The unintended side effect is that they often insert differences in behavior from functional software verification - or the Intellectual Property (IP) block simulation models do not match behavior in silicon. This leaves the designer with no other option - they must see their design working on the chip.
Today, the most prevalent method of seeing the design work in silicon is to use a prototype board or just debug in-system in the lab. Making the shift from the software verification world to the lab removes the flexibility and debugging power of a software simulator. Lab tools are like debugging a vast world through a keyhole! As the chips get bigger, the world is bigger - this approach is not productive - it is a non-starter.
The best solution for this conundrum is to bring the FPGA into the simulator like GateRocket does with the RocketDrive. This solution gives the user unparalleled FPGA verification productivity and as the chips get bigger, so naturally the solution scales.
Let the chips become mammoth, that's more for us to innovate with!