Debugging Big FPGAs on Fat Tuesday at DVCon
Posted by Dave Orecchio on Thu, Feb 26, 2009 @ 01:42 PM
Tuesday of this week was Fat Tuesday, the last day of Mardi Gras and it was also the first day of the Design Verification Conference (DVCon) in San Jose, CA.
GateRocket was there with their Mardi Gras beads, demos and more to show the leading design verification engineers the best way to verify and debug the biggest and fattest FPGAs on the planet.
Of course the conference sports the usual ASIC designers, but the majority of the attendees were using FPGAs in their verification process for ASICs or as a central part of their product.
Each of them experienced challenges getting their designs to work in the lab. GateRocket demonstrated the new Device Native verification approach for FPGA verification and debug to packed crowds. They say the conference attendance was down this year but GateRocket was very busy throughout the two exhibition days.
If you missed the action at DVCon and want to learn how to debug a Big Fat FPGA, register for a webinar.