FPGA projects dominate by a 30 to 1 margin
Posted by Dave Orecchio on Mon, Mar 30, 2009 @ 12:15 PM
Gartner announced today that FPGA projects are dominating ASIC projects by a 30 to 1 margin. The global economic climate will result in a 22% decrease in ASIC projects in 2009. This is the second year in a row with significant declines in ASIC projects.
The general wisdom as discussed in the EE-Times article is that for all but the highest volume projects FPGAs is the technology choice. In my earlier post titled "Mamouth FPGAs Require New Tools", the FPGA technology trend is shows the increase in capacity and performance in the most recent two years. This change is a key factor for the shift in design projects because, without an option the design teams would have stayed with ASIC technology but now that they have an option - they are going with the lower risk, lower cost and faster time-to-market chip technology choice.
FPGA tools are constantly changing. They have to in order to optimize the performance of the design on each specific FPGA architecture. Unlike ASIC where one tool fits all, FPGA synthesis or Place and Route for example must make effective use of the FPGA resources in order to maximize performance of the design on the FPGA. The constant change in these tools is the source for errors which are only found in the lab, the very bugs that require countless re-spins of the FPGA in the lab to discover them.
GateRocket is focused on the growing FPGA market and specifically solving the verification and debug problem. We minimize the risk of using the large FPGAs by identifying issues before you get into the lab, when they are the least costly and time consuming to fix. Check out our whitepaper to learn how.