FPGA Tools Need a Bailout
Posted by Dave Orecchio on Mon, Apr 20, 2009 @ 11:45 AM
You don't have to be a Wall Street tycoon to deserve a bailout!
Stuck in a sub-prime FPGA program-test-reprogram debug style? Counting on equity
in your tester-side lab bench to find bugs? Are long-chain test patterns
trashing your simulator credit score?
Every FPGA
designer should have the opportunity to deliver designs on time, on spec and
bug-free. Design tools that are fast, accurate and address the unique issues
facing FPGA designers shouldn't be check boxes on some wish list.
FPGA tools are badly in need of a bailout.
Not the kind of bailout offered by the federal government (according to the Motley Fool the government bailout cost is topping $10T), more like a significant improvement in the FPGA tools used to test the design implemented in silicon while exercised in the simulator and a methodology to shorten the endless lab bring-up cycle.
The problem with FPGA tools for the lab is that they require the design to work - at least partially - in order to get any meaningful data. Secondly, you have to know where to look and have an idea what causes the problem else you are in the repetitive test - synthesize, place and route the FPGA - retest cycle.
If the designer had the ability to see the bugs in the silicon while inside the simulation environment they would gain direct visibility of a bug location in an interactive environment when it is easiest to fix early in the design process. Bugs that slip from the front of the design process to the system in the lab is like water gushing in from a large hole in the bottom of the boat.
Don't just bail out the bugs, eliminate them at the source when they occur, up front in the design process. Check out GateRocket's Device Native verification solution and see how it is done.