DAC Technical Sessions That Appeal to FPGA Designers
Posted by Dave Orecchio on Thu, Jul 09, 2009 @ 11:24 AM
Guest post by:Andrew B. Kahng,
General Chair, 46th Design Automation Conference.
DAC’s Technical Program this year was developed with great care and should offer something for every designer practicing in our industry. FPGAs can be found in the rapid turnaround segment of the electronics market. In addition, they have permeated the prototyping environment in SOC design. Many technical events at DAC will be of interest to designers who use advanced FPGA devices.
For starters, I would like to draw your attention to a best paper nominee, “A Computing Origami: Folding Streams in FPGAs,” in Session 18. The paper will describe the concept of “folding” streams onto FPGA coprocessors to create efficient design implementations. FPGAs form the central focus of Session 17, “Leveraging Parallelism in FPGAs and Multicore Systems.” This session will cover a comprehensive set of topics focusing on hardware parallelism using FPGAs and multicore computing, two timely subjects for DAC attendees. One paper will present a novel two-tier coarse grain reconfigurable architecture to reduce power and improve performance. Another paper will detail a way to estimate switching activity and reduce power in FPGAs during high-level synthesis. Yet another paper will present a practical application –– accelerating simulation of wireless systems –– using FPGAs. The session, to be held Thursday from 2-4 p.m., will conclude with a presentation showing how FPGAs can be used in hardware-accelerated parallel processing.
Of interest to FPGA designers will be the panel, “System Prototypes: Virtual, Hardware or Hybrid?,” that takes place Tuesday from 10:30 a.m.-noon. Chaired by Ron Wilson, it will explore various forms of prototyping in the SoC design cycle. Will the recent emergence of virtual prototypes signal the end of FPGA-based approaches? Or will the hardware based prototypes continue to survive?
DAC will also offer 19 panels throughout the week in the DAC Pavilion (Booth #1928) in the Exhibit Hall. One session of particular interest to startups and consumers of EDA tools, FPGA-based or otherwise, will be chaired by Lucio Lanza of Lanza Tech Ventures and will be held Tuesday from 1-2 p.m. Lucio will host a Town Hall Meeting that will attempt to answer, “Can We Afford for Start-Ups to Wind Down?,” with panelists from Intel Capital, Needham & Company and Denali. According to Lanza, the economic crisis has strangled investment for semiconductor startups. The lack of industry growth and IPOs, rising design costs, and alternative investment opportunities have all served to starve these engines of innovation. Given the impact of the crisis on the startup model, this panel will consider the resulting long-term health of the semiconductor industry.
On a more positive note, the DAC Exhibit Hall –– with approximately 200 vendors, the Exhibitor Forum, the IC Design Central Pavilion and the already-noted Pavilion –– should be bustling with activity all week long. Startups such as GateRocket (Booth 3550), who’s leading the way in the increasingly important area of FPGA-based verification, will help create a buzz. GateRocket and others continue to bring innovation and change to the both the EDA industry and production semiconductor design methodologies.
With so much going on, you can’t afford to miss DAC in San Francisco later this month. I look forward to seeing you there.