Top FPGA Verification and Debug Issues	How GateRocket Can Help
	GateRocket cuts system debug time in half by making simulation silicon-accurate and thereby exposing problems that would otherwise slip through to the system lab where they are much harder to find and fix. The RocketVision debug environment also provides full visibility of the FPGA signals during debugging - in stark contrast to the limitations of on-chip logic analyzers.
	GateRocket cuts the number of FPGA builds (Synthesis + PAR) in half with its unique RocketVision "soft-patch" capability that lets you make changes to a specific RTL block and run it with the rest of the chip modeled in FPGA harware. In this way you can test fixes without rebuilding the FPGA and find/fix multiple bugs per day.
	By exploiting the speed of native FPGA hardware, the RocketDrive accelerates simulation run times by an average of 4 - 10x or more without changing your methodology and thereby helps you find more bugs in less time. That's especially important when simulating long unbreakable test sequences that can't be split up on a simulation farm.
	With its RocketVision debug environment GateRocket automatically detects any differences between your simulation model and the FPGA hardware implementation, thereby saving you weeks of debugging time. These differences often result from inconsistencies in the models for complex IP blocks and from errors in the synthesis process.